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Main.vhd

Hlavní modul

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:18:51 04/11/2019 
-- Design Name: 
-- Module Name:    Main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Main is
    Port ( CLK 			: in  STD_LOGIC;
           LED 			: out  STD_LOGIC_VECTOR (7 downto 0));
end Main;

architecture Behavioral of Main is

-- definice potrebnych signalu logiky posunu
signal clk_div   			: std_logic_vector(22 downto 0);
signal prvniShreg			: std_logic_vector(7 downto 0) := B"00000001";
signal druhyShreg			: std_logic_vector(7 downto 0) := B"00000010";
signal tretiShreg			: std_logic_vector(7 downto 0) := B"00000100";
signal prvniSmer  		: std_logic := '1';
signal druhySmer			: std_logic := '1';
signal tretiSmer			: std_logic := '1';

-- signaly intenzity sviceni
signal prvniIntenzita	: std_logic_vector(7 downto 0) := B"10000000";	-- 50%
signal druhaIntenzita	: std_logic_vector(7 downto 0) := B"00000000";	-- 100%
signal tretiIntenzita	: std_logic_vector(7 downto 0) := B"10000000";	-- 50%
signal prvniLED			: std_logic;
signal druhaLED			: std_logic;
signal tretiLED			: std_logic;

component PWM is
    Port ( CLK 			: in  STD_LOGIC;
           PWM_in 		: in  STD_LOGIC_VECTOR (7 downto 0) := "10000000";
           PWM_out 		: out  STD_LOGIC);
end component;

begin
PWM1: PWM
	Port map( CLK => CLK, PWM_in => prvniIntenzita, PWM_out => prvniLED );
	
PWM2:	PWM
	Port map( CLK => CLK, PWM_in => druhaIntenzita, PWM_out => druhaLED );

PWM3:	PWM
	Port map( CLK => CLK, PWM_in => tretiIntenzita, PWM_out => tretiLED );
	
-- definovat 3 bitovy vektor intenzity sviceni
	
    -- deleni hodin
	process (CLK)
    begin
        if (CLK'Event and CLK = '1') then
            clk_div <= clk_div + '1';
        end if;
    end process;


	-- zpracovani posunu LEDky a prirazeni LED s danou intenzitou
    process (clk_div(22), prvniLED, druhaLED, tretiLED)
    begin
        if (clk_div(22)'Event and clk_div(22) = '1') then
				-- posun doprava 1. LED:
            if (prvniSmer = '1') then
                prvniShreg <= prvniShreg(6 downto 0) & '0';
                if (prvniShreg = X"40") then
                    prvniSmer <= '0';
                end if;
			   -- posun doleva 1. LED:
            else
                prvniShreg <= '0' & prvniShreg(7 downto 1);
                if (prvniShreg = X"02") then
                    prvniSmer <= '1';
                end if;
            end if;
				
				-- posun doprava 2. LED:
				if (druhySmer = '1') then
					 druhyShreg <= druhyShreg(6 downto 0) & '0';
					 if (druhyShreg = X"40") then
						  druhySmer <= '0';
					 end if;
				-- posun doleva 2. LED:
				else
					 druhyShreg <= '0' & druhyShreg(7 downto 1);
					 if (druhyShreg = X"02") then
						  druhySmer <= '1';
					 end if;
				end if;
				
				-- posun doprava 3. LED:
				if (tretiSmer = '1') then
					 tretiShreg <= tretiShreg(6 downto 0) & '0';
					 if (tretiShreg = X"40") then
					     tretiSmer <= '0';
				    end if;
				-- posun doleva 3. LED:
				else
					 tretiShreg <= '0' & tretiShreg(7 downto 1);
					 if (tretiShreg = X"02") then
						  tretiSmer <= '1';
					 end if;
			   end if;
        end if;
    end process;


	 -- zobrazeni vysledku na LEDky
	 LED <= prvniShreg or druhyShreg or tretiShreg;

end Behavioral;

Neformátovaný

Přidáno: 4.5.2019
Expirace: Neuvedeno

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Autor: Lolindir
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