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PWM.vhd

Modul pulzní modulace (PWM)

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:02:40 05/02/2019 
-- Design Name: 
-- Module Name:    PWM - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PWM is
    Port ( clk : in  STD_LOGIC;
           PWM_in : in  STD_LOGIC_VECTOR (7 downto 0) := "10000000";  -- intenzita svícení
           PWM_out : out  STD_LOGIC);		-- jedna LED, které měníme intenzitu
end PWM;

architecture PWM_arch of PWM is
	signal  PWM_Accumulator : std_logic_vector(8 downto 0);

begin

  process(clk, PWM_in)
  begin
    if rising_edge(clk) then      
      PWM_Accumulator  <=  ('0' & PWM_Accumulator(7 downto 0)) + ('0' & PWM_in);
    end if;
  end process;

  PWM_out <= PWM_Accumulator(8);
end PWM_arch;

Neformátovaný

Přidáno: 4.5.2019
Expirace: Neuvedeno

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Autor: Lolindir
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